Each memory cell in a memory array of a dynamic random access memory (DRAM) structure includes a charge-storage capacitor element and a MOSFET controlling input into and output from the capacitor element. Stored information is represented by the charge across the capacitor element. This charge decays over time due to MOSFET leakage current and to charge recombination on the surface of the semiconductor substrate. Therefore, a process of periodically "refreshing" stored information is required. For accomplishing refresh processing at high efficiency, a number of refresh modes have been developed. One common technique is referred to as the "CAS (Column Address Strobe) Before RAS (Row Address Strobe)" (CBR) refresh mode in which start of refresh is signalled by switching the timing order of the system generated RAS and CAS signals from that of a normal operating mode.
To enhance versatility, a "sleep mode" is designed into many random access memories. An externally applied CAS before RAS transition thus initiates sleep mode and thus self-refreshing of the memory array. Self-timed refreshing of the memory array typically utilizes a Row Address Counter (RAC), also referred to as a RAC counter, to track refreshing of the memory array and the mode is maintained as long as the system generated RAS signal is held constant.
Implementation of an integrated, self-timed refresh circuit within a semiconductor memory device raises three concerns. First, with any refresh circuit implementation it is highly desirable to maintain specified product timing parameters so that performance of the memory device does not deteriorate. Second, data integrity of the memory device must be maintained by compensating self-timed refresh intervals with changes in process and operating conditions. For example, if temperature increases, the memory cells become leakier and, thus, it is desirable to refresh the memory array more often. Third, "non-invasive" functional verification of memory device performance is desired, which also minimizes test time. Presently, there is no known self-timed refresh circuit and testing method which adequately address all of these concerns.
Thus, a novel, programmable self-timed refresh circuit for integrating with a random access memory, which is susceptible to "non-invasive" and deterministic testing methods for accurate programming and testing of the refresh rate and wait state interval of the refresh mode, will significantly advance the state-of-the-art. The present invention provides such circuitry and programming/testing methods.